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HN27C4000G Series
524288-Word x 8-Bit/262144-Word x 16-Bit CMOS UV Erasable and Programmable ROM
Description
The Hitachi HN27C4000 is a 4-Mbit UV erasable and electrically programmable ROM that is organized either as 524288-word x 8-bit or as 262144-word x 16 bit, featuring extra-high speed burst mode that gives two times faster 4-word or 8-byte serial access than normal. And also high speed and fast programming are served as well as the existing Hitachi 4M device HN27C4096 and HN27C4001. Fabricated on advanced fine process and high speed circuitry technique, HN27C4000 makes high speed access time and low power dissipation in either active or stand-by mode. Therefore, it is suitable for all systems featuring high speed microprocessor such as the 80386, 80486, 68030, 68040 and so on.
Features
* Organization: 524288-word x 8-bit/262144-word x 16-bit (BYTE/VPP enables selection byte-wide or word-wide) * High speed: Access time 100 ns/120 ns/150 ns (max) Burst access time 50 ns/60 ns/60 ns (max) * Low power dissipation: Standby mode; 5 W (typ), Active mode; 150 mW/MHz (typ) * Fast high reliability page programming, fast high-reliability programming and option programming: Program voltage; +12.5 V DC Program time; 3.5 sec (min) (Theoretical in Page programming) * Inputs and outputs TTL compatible during both read and program modes * Pin arrangement: 40-pin EIAJ standard pin compatible with HN62414/ HN62434 * Device identifier mode: Manufacturer code and device code
Ordering Information
Type No. HN27C4000G-10 HN27C4000G-12 HN27C4000G-15 Access Time 100 ns 120 ns 150 ns Package 600-mil 40-pin cerdip (DG-40A)
HN27C4000G Series
Pin Arrangement
HN27C4000G Series A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC
(Top view)
Pin Description
Pin Name A0 - A17 I/O0 - I/O14 I/O15/A-1 CE OE VCC BYTE/V PP VSS Function Address Input/output Input/output/address Chip enable Output enable Power supply Byte/word selection/ Programming power supply Ground
2
HN27C4000G Series
Block Diagram
A7 : : : : : : : : : : : : A17
XDecoder
2,048 x 2,048 Memory Matrix
I/O0 : : :
I/O15
Input Data Control
Y-Gating Y-Decoder
CE OE VCC V PP VSS
H
A0 . . . . . . . . . . . . . A6
H
: High threshold inverter
3
HN27C4000G Series
Mode Selection
Pin DG-40A CE OE A9 BYTE/V PP (10) (12) (39) (31) VIL VIL VIL VIL VIH Page program set Page data latch Page program Page program verify VIH VIL VIL VIH VIL VIL VIH VIH X VH VH
*2 *2
Mode Read (X16 bit) Read (X8 bit) Output disable (X16 bit) Output disable (X8 bit) Standby Page prog.
I/O0 - I/O8 - I/O15/ VCC I/O7, I/O14, A-1 (21) (13 - 20, 22 - 28, 29) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Dout Dout High-Z High-Z High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code Dout High-Z High-Z High-Z High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code Dout VIH/V IL High-Z VIH/V IL High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code
X X X X X X X X X X X X X X VH
*2
VIH VIL VIH VIL VSS - VCC VPP VPP VPP VPP VCC VPP VPP VPP VPP VSS - VCC
VIH VIL VIH VIH VIL VIL VIH VIL
Page program reset VIH Word prog. Program Program verify Optional verify Program inhibit Identifier Notes: 1. X: Don't care. 2. VH : 12.0 V 0.5 V VIL VIH VIL VIH VIL
Absolute Maximum Ratings
Parameter All input and output voltages Voltage on pin A9 and OE VPP voltage VCC voltage
*1 *1 *1
Symbol Vin, Vout VID VPP VCC Topr Tstg Tbias
*3
Value -0.6 to +7.0 -0.6 to +13.0 -0.6 to +13.5 -0.6 to +7.0 0 to +70 -65 to +125 -20 to +80
*2 *2
Unit V V V V C C C
Operating temperature range Storage temperature range
Storage temperature under bias
Notes: 1. Relative to VSS . 2. Vin, Vout, V ID min = -2.0 V for pulse width 20 ns 3. Storage temperature range of device before programming.
4
HN27C4000G Series
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 12 20 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V Notes Except BYTE/V PP
Read Operation
DC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C)
Parameter Input leakage current Output leakage current VPP current Standby V CC current Symbol I LI I LO I PP1 I SB1 I SB2 Operating VCC current I CC1 I CC2 Input voltage VIL VIH Output voltage VOL VOH Min -- -- -- -- -- -- -- -0.3 2.2 -- 2.4
*1
Typ -- -- 1 -- 1 -- -- -- -- -- --
Max 2 2 20 1 20 35 120 0.8 VCC + 1 0.45 --
*2
Unit A A A mA A mA mA V V V V
Test Conditions Vin = 5.5 V Vout = 5.5 V/0.45 V VPP = 5.5 V CE = VIH CE = VCC 0.3 V Iout = 0 mA, f = 1 MHz Iout = 0 mA, f = 10 MHz
I OL = 2.1 mA I OH = -400 A
Notes: 1. VIL min = -1.0 V for pulse width 50 ns VIL min = -2.0 V for pulse width 20 ns 2. VIH max = VCC +1.5 V for pulse width 20 ns If V IH is over the specified maximum value, read operation cannot be guaranteed.
5
HN27C4000G Series
AC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C) Test Conditions * * * * Input pulse levels: 0.45 to 2.4 V Input rise and fall time: 10 ns Output load: 1 TTL gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V
HN27C4000 -10 Parameter Address to output delay CE to output delay OE to output delay Burst address to output delay OE high to output float Note:
*1
-12 Max 100 100 60 50 35 -- Min -- -- -- -- 0 5 Max 120 120 60 60 40 --
-15 Min -- -- -- -- 0 5 Max 150 150 70 60 50 -- Unit ns ns ns ns ns ns Test Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = VIL CE = OE = VIL
Symbol Min t ACC t CE t OE t BAC t DF t OH -- -- -- -- 0 5
Address to output hold
1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Read Timing Waveform
Address
CE
Standby mode tCE
Active mode
Standby mode
OE tOE t ACC Data Out Data Out Valid tOH
tDF
6
HN27C4000G Series
Read Timing Waveform (Burst access mode)
In Burst Access mode, fast read-out of 4 word data is selected by address A0, A1. (Valid only for Read x 16 mode)
A2 to A17
t ACC t CE
CE
t OE
OE
t BAC t BAC tBAC tBAC
A0, A1
t OH t OH Valid Output t OH Valid Output t OH Valid Output
Data Out
Valid Output
In Burst Access mode, fast read-out of 8 byte data is selected by address A-1, A0, A1. (Valid only for Read x 8 mode)
A2 to A17
t ACC t CE
CE
t OE
OE
tBAC t BAC tBAC tBAC tBAC tBAC tBAC tBAC
A-1, A0, A1
t OH t OH
Valid Output
t OH
Valid Output
t OH
Valid Output
t OH
Valid Output
t OH
Valid Output
t OH
Valid Output
t OH
Valid Output
Data Out
Valid Output
7
HN27C4000G Series
Fast High-Reliability Page Programming
This device can be applied the high performance page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. Page Program Set Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode. The device operates in a page program mode until reset. Page Program Reset Set VPP to VCC level or less to reset a page program mode.
8
HN27C4000G Series
START SET PAGE PROG LATCH MODE VPP= 12.5 0.3 V V = 6.25 0.25 V CC OE = 12.0 0.5 V Address = 0 n=0 Latch Address + 1 Address Latch Address + 1 Address Latch Address + 1 Address Latch n + 1 n SET PAGE PROG./VERIFY MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address + 1 Address Program tPW = 50 s 5% VERIFY NO GO LAST address? NOGO
n = 10? YES
NO
YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address GO END Fast High-Reliability Page Programming Flowchart NOGO
FAIL
9
HN27C4000G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Parameter Input leakage current Output voltage during verify Symbol I LI VOL VOH Operating VCC current Input voltage I CC VIL VIH VH VPP supply current I PP Min -- -- 2.4 -- -0.1 2.2 11.5 --
*5
Typ -- -- -- -- -- -- 12.0 --
Max 2 0.45 -- 50 0.8 VCC + 0.5 12.5 70
*6
Unit A V V mA V V V mA
Test Conditions Vin = 6.5 V/0.45 V I OL = 2.1 mA I OH = -400 A
CE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while V PP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
10
HN27C4000G Series
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timing: Inputs; 0.8 V, 2.0 V, Outputs; 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time VPP hold time
*2
Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1
Typ -- -- -- -- -- -- -- -- 50.0 -- -- -- -- -- --
Max -- -- -- -- -- 130 -- -- 52.5 -- 150 -- -- -- --
Unit s s s s s ns s s s s ns s s s s
Test Conditions
t VPS t VCS
CE initial programming pulse width t PW t CES t OE t LW t OHS t OHH t VRS
Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when V PP is set to VCC or less.
11
HN27C4000G Series
Fast High-Reliability Page Programming Timing Waveform
Page program mode Program data latch A2 - A17 t AS A0, A1 t DH t DS Data Data in stable Data out valid t VPS VPP
VPP VCC
Page program
Program verify
t AH
t AS
t AH
t OE t DF
t VCS
VCC + 1.25
VCC
VCC
t OHH t OHS t CES t PW t OES
CE t LW OE
VH VIH VIL
t VRS
12
HN27C4000G Series
Fast High-Reliability Programming This device can be applied the fast high-reliability programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data.
START SET PROG./VERIFY MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address = 0 n=0 n+1 n
Program tPW = 50 s 5% Address + 1 Address NO VERIFY GO LAST address? NOGO n = 10? YES NO
YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address GO END NOGO
FAIL
Fast High-Reliability Programming Flowchart
13
HN27C4000G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP =12.5 V 0.3 V, Ta=25C 5C)
Parameter Input leakage current VPP supply current Operating VCC current Input voltage Symbol I LI I PP I CC VIL VIH Output voltage VOL VOH Min -- -- -- -0.1 2.2 -- 2.4
*5
Typ -- -- -- -- -- -- --
Max 2 40 50 0.8 VCC + 0.5 0.45 --
*6
Unit A mA mA V V V V
Test Conditions Vin = 6.5 V/0.45 V CE = VIL
I OL = 2.1 mA I OH = -400 A
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timings: 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE to output float delay VPP setup time VCC setup time Data valid from OE Note: Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 0
Typ -- -- -- -- -- -- -- -- 50.0 --
Max -- -- -- -- -- 130 -- -- 52.5 150
Unit s s s s s ns s s s ns
Test Conditions
t VPS t VCS
CE initial programming pulse width t PW t OE
1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
14
HN27C4000G Series
Fast High-Reliability Programming Timing Waveform
Program Address t AS Data t DS V PP V PP V CC t VPS V CC V CC+1.25 V CC t VCS CE Data In Stable t DH t AH Data Out Valid t DF Program Verify
t PW OE
t OES
t OE
Optional Page Programming
This device can be applied the optional page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. This programming algorithm is the combination of page programming and word verify. It can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. Regarding the timing specifications for page programming and word verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming.
15
HN27C4000G Series
START SET PAGE PROG LATCH MODE VPP= 12.5 0.3 V V = 6.25 0.25 V CC OE = 12.0 0.5 V Address = 0 Latch Address + 1 Latch Address + 1 Latch Address + 1 Latch SET PAGE PROG. MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address + 1 Address Program tPW = 50 s 5% NO LAST address? Address Address Address
YES PAGE PROG. RESET VPP = VCC = 6.25 0.25 V SET WORD PROG./VERIFY MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address = 0 n=0 VERIFY NOGO n+1 Address + 1 Address n Program tPW = 50 s 5% VERIFY GO LAST all address? YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address GO END FAIL NOGO n = 10? YES NO NOGO
GO
Optional Page Programming Flowchart
16
HN27C4000G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP =12.5 V 0.3 V, Ta = 25C 5C)
Parameter Input leakage current Output voltage during verify Symbol I LI VOL VOH Operating VCC current Input voltage I CC VIL VIH VH VPP supply current I PP Min -- -- 2.4 -- -0.1 2.2 11.5 --
*5
Typ -- -- -- -- -- -- 12.0 --
Max 2 0.45 -- 50 0.8 VCC + 0.5 12.5 70
*6
Unit A V V mA V V V mA
Test Conditions Vin = 6.5 V/0.45 V I OL = 2.1 mA I OH = -400 A
CE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
17
HN27C4000G Series
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timings: Inputs; 0.8 V, 2.0 V Outputs; 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time Page programming reset time VPP hold time
*2 *2
Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1 1
Typ -- -- -- -- -- -- -- -- 50.0 -- -- -- -- -- -- --
Max -- -- -- -- -- 130 -- -- 52.5 -- 150 -- -- -- -- --
Unit s s s s s ns s s s s ns s s s s s
Test Conditions
t VPS t VCS
CE initial programming pulse width t PW t CES t OE t LW t OHS t OHH t VLW t VRS
Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when V PP is set to VCC or less.
18
HN27C4000G Series
Option Page Programming Timing Waveform
Page program mode Program data latch Page program
Word program mode Program verify Program
A2 - A17 t AH t AS t AH t AS t AH
A0, A1 t DS
Data in stable
t DH t DS
Data out valid
t DF
Data in stable
Data t VPS VPP VCC t VCS
t VPS t OE t DF
VPP
t VRS t VLW
VCC+ 1.25 VCC VCC t OHS t OHH t CES
t CES
CE t LW t PW OE VH VIH VIL
t OES t PW
Erase Erasure of this device is performed by exposure to ultraviolet light of 2537 A and all the output data are changed to "1" after this erasure procedure. The minimum integrated dose (i.e. UV intensity X exposure time) for erasure is 15 W * sec/cm2.
19
HN27C4000G Series
Mode Description
Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C4000G Identifier Code
DG40A A0 (9) VIL VIH I/O8 - I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 -- (28) (26) (24) (22) (19) (17) (15) (13) Hex Data X X 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 1 07 A1
Identifier Manufacturer code Device code Notes: 1. 2. 3. 4. 5.
VCC = 5.0 V 10% A9 = 12.0 V 0.5 V CE, OE = VIL A1 - A8, A10 - A17: Don't care. X: Don't care.
20
HN27C4000G Series
Package Dimensions
HN27C4000G Series (DG-40A)
Unit: mm
40
52.07 53.34 Max 8.89
21 15.51 Max 2.54 Min 6.30 Max 14.66 20 0.51 Min
15.24
1
1.32 2.54 Max
2.54 0.25
0.48 0.10
0 - 10
0.25- 0.05
+ 0.11
21

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